1. Field of the Invention
The present invention relates generally to a time-division bit number conversion circuit and, more particularly, is directed to a time-division bit number conversion circuit suitably applied to, for example, an input/output portion of each of digital signal processing portions of a digital television receiver.
2. Description of the Prior Art
FIG. 1 shows an example of a prior-art television receiver.
Referring to FIG. 1, it will be seen that a luminance signal Y applied to an input terminal 62Y is converted to a digital signal by an analog-to-digital (A/D) converter 63Y and is fed to a scanning line interpolating circuit 65Y. A sampling frequency fs in the A/D converter 63Y is selected to be, for example, 14 MHz.
Red and blue color difference signals R-Y and B-Y applied to input terminals 62R and 62B are respectively converted to digital signals by A/D converters 63R and 63B, and are then fed to fixed contacts R and B of a change-over switch 64, respectively. The change-over switch 64 is alternately connected to the fixed contacts R and B at every sampling cycle. A time-division signal R-Y/B-Y of the red and blue color difference signals R-Y and B-Y from the change-over switch 64 is supplied to a scanning line interpolating circuit 65C.
The scanning line interpolating circuits 65Y and 65C generate scanning line signals Yc and Rc-Yc/Bc-Yc in addition to main scanning line signals Ym and Rm-Ym/Bm-Ym simultaneously.
The luminance signal Y from the A/D converter 63Y is supplied to a moving detection circuit 50, and a moving detection signal from the moving detection circuit 50 is supplied to a coefficient generator 51. Value K of multipliers in the scanning line interpolating circuits 65Y and 65C is generated by the coefficient generator 51, and the value K is changed in response to the level of the moving detection signal. For example, K=0 is established for the still picture portion and the maximal value K is 1.
FIG. 2 shows more in detail the arrangement of the moving detection circuit 50 in FIG. 1.
Referring to FIG. 2, it will be seen that the luminance signal Y from the A/D converter 63Y (FIG. 1) is supplied to a series circuit of field memories 401 and 402 forming a delay line. The delay time of the serially-connected field memories 401 and 402 is selected to be one frame (263H+262H).
The input signal to the field memory 401 and the output signal from the field memory 402 are supplied to a subtracter 403 and are thereby subtracted each other. The frame difference signal from the substracter 403 is supplied to a low-pass filter 404, in which a high band noise component and a dot interference component of the frame difference signal are eliminated. The frame difference signal thus processed is supplied to an absolute value circuit 405, in which it is converted to an absolute value signal. The output signal from the absolute value circuit 405 is employed as the moving detection signal.
The scanning line interpolating circuit 65Y is constructed as shown in FIG. 3.
Referring to FIG. 3, it will be seen that the luminance signal Y from the A/D converter 63Y (FIG. 1) is supplied to a line memory 601 (1 H delay time) forming a delay line. The input and output signals of the line memory 601 are supplied to an adder 602, in which they are added and averaged. The thus averaged output signal from the adder 602 is multiplied by K (K.ltoreq.1) by a multiplier 603, and is then fed to an adder 604.
The luminance signal Y is also supplied to a field memory 605 forming a delay line. The delay time of the field memory 605 is selected to be 263H. The output signal from the field memory 605 is multiplied by (1-K) by a multiplier 606 and is then fed to the adder 604.
FIG. 4 is a schematic diagram showing a scanning line structure from a time-vertical surface standpoint, in which an open circle represents the scanning line of each field. Assuming that h is the above-mentioned input signal, i the output signal from the line memory 601 and j the output signal from the field memory 605, then these signals h to j are plotted in a positional relationship shown in FIG. 4.
In the scanning line interpolating circuit 65Y, an output signal ##EQU1## of the adder 602 forms an interpolating scanning line signal of a real moving picture portion, and the output signal j of the field memory 605 forms an interpolating scanning line signal of a still picture portion. Thus, the adder 604 generates an interpolating scanning line signal Yc in which the interpolating scanning line signals of the real moving picture portion and the still picture portion are added at a ratio corresponding to the amount of the movement. The scanning line to be interpolated is set at a position shown by a broken line circle shown in FIG. 4. The input signal h is directly used as the main scanning line signal Ym.
The scanning line interpolating circuit 65C is constructed similarly to the scanning line interpolating circuit 65Y and therefore need not be described herein.
Referring back to FIG. 1, the main scanning line signals Ym, Rm-Ym/Bm-Ym and the interpolating scanning line signals Yc, Rc-Yc/Bc-Yc from the scanning line interpolating circuits 65Y and 65C are supplied to timebase-compressing circuits 67Y and 67C, respectively. The timebase-compressing circuits 67Y and 67C timebase-compress the main scanning line signals Ym, Rm-Ym/Bm-Ym and the interpolating scanning line signals Yc, Rc-Yc/Bc-Yc by half, which are then delivered sequentially. In this case, the timebase-compressing circuit 67C generates the red and blue color difference signals, separately.
The double-speed luminance signal and color difference signals from the timebase-compressing circuits 67Y and 67C are converted to analog signals by digital-to-analog (D/A) converters 68Y, 68R and 68B, respectively.
The double-speed luminance signal and color difference signals from the D/A converters 68Y, 68R and 68B are supplied to a matrix circuit 73. The double-speed red, green and blue signals R, G and B from the matrix circuit 73 are respectively supplied through amplifiers 74R, 74G and 74B to a color cathode ray tube (color CRT) 75, whereby a video image is displayed on the color CRT 75 according to the non-interlaced system in which the number of scanning lines is doubled.
In the prior-art television receiver shown in the example of FIG. 1, the luminance signal Y and the color difference signals R-Y and B-Y are generated from a television tuner (not shown). If the bands of the color difference signals R-Y and B-Y are narrow, then the numbers of samples of, for example, the color difference signals R-Y and B-Y are selected to be 1/4 of the number of samples of the luminance signal Y, thus resulting in a so-called 4:1:1 mode. In that event, when the luminance signal Y from the A/D converter 63Y is represented as shown in FIG. 5A, then the time-division signal R-Y/B-Y from the change-over switch 64 becomes as shown in FIG. 5C.
If the bands of the color difference signals R-Y and B-Y are wide, then the numbers of samples of, for example, the color difference signals R-Y and B-Y are made 1/2 of the number of samples of the luminance signal Y, thus resulting in a so-called 4:2:2 mode. In this case, the time-division signal R-Y/B-Y from the change-over switch 64 becomes as shown in FIG. 5B.
Regardless of the 4:1:1 mode or the 4:2:2 mode, the A/D converters 63R and 63B convert the color difference signals into digital signals in the form of, for example, 8 bits per sample.
The video memory of large capacity used in the scanning line interpolating circuit 65C is generally of 4 bits so that even in the 4:1:1 mode, it is necessary to provide two memories, or a memory of 8 bits. Thus, the memory can not be effectively utilized, which provides an increased circuit scale.
Even in the 4:1:1 mode, the digital signal is transmitted in the unit of 8 bits, thus increasing the pattern area on the substrate.